By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

ISBN-10: 3319139053

ISBN-13: 9783319139050

ISBN-10: 3319139061

ISBN-13: 9783319139067

This monograph is predicated at the 3rd author's lectures on machine structure, given in the summertime semester 2013 at Saarland college, Germany. It encompasses a gate point development of a multi-core laptop with pipelined MIPS processor cores and a sequentially constant shared memory.

The e-book comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and in addition of a cache established sequentially constant shared reminiscence. This opens how one can the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and therefore deterministic. against this the reference versions opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.

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Additional resources for A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof

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By induction on n. If n = 0, then s is an input and s(a) is clearly well defined by the first rule. If n > 0, then we have d(in1(s)) < n. If s is not an inverter, we also have d(in2(s)) < n. By induction hypothesis in1(s)(a) and in2(s)(a) (for the case if s is not an inverter) are well defined. We now conclude that s(a) is well defined by the second and third rules. 2 Some Basic Circuits Boolean expressions can be translated into circuits in a very intuitive way. In Fig. 5(b) we have translated the simple formulas from (4) for c (a, b, c) and s(a, b, c) into a circuit.

5 hold in cycle c for all signals with depth 0: ∀t ∈ [e(c) + σ, e(c + 1) + ρ] : x[i](t) = x[i]c , then the same statement holds for all signals y in cycle c: ∀y : ∀t ∈ [e(c) + tmax(y), e(c + 1) + tmin(y)] : y(t) = y c . Proof. By induction on the depth d(y) of signals. Let the statement hold for signals of depth d − 1 and let y be a ◦-gate of depth d. We show that it holds for y. Consider Fig. 24. There are inputs z1 , z2 of y such that d(y) = d(z1 ) + 1 ∧ sp(z) = sp(z2 ) + 1 . Hence, tmax(y) = tmax(z1 ) + β tmin(y) = tmin(z2 ) + α .

In a hardware computation, we count cycles (steps of the digital model) using natural numbers t ∈ N ∪ {−1}. The hardware configuration in cycle t of a hardware computation is denoted by ht = xt [n − 1 : 0] and the value of signal y during cycle t is denoted by y t . The values of the reset signal are fixed. 3 Clocked Circuits 43 0 1 0 x[1] reset 1 y Fig. 19. Simple clocked circuit with a single register resett = 1 t = −1 0 t≥0. At power up, register values are binary but unknown. We denote this sequence of unknown binary values at startup by a[n − 1 : 0]: x−1 [n − 1 : 0] = a[n − 1 : 0] ∈ Bn .

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A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul


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